Modern integrated circuitry relies on complex manufacturing processes to create such circuitry. Such may ultimately result in defective portions of circuitry, for example such as defective logic circuits, defective memory cells, defective access lines, or defective digit lines. One technique used to account for potential defects is to build in redundant circuitry, for example redundant rows of access lines and redundant columns of digit lines. In some instances, an antifuse cell comprising a transistor and an antifuse element may be used, for example, to provide a programmable electrical coupling connection to a portion of the redundant circuitry by “blowing” the antifuse element. Additionally, antifuse cells comprising a transistor and an antifuse element may be used in other existing or yet-to-be-developed implementations not necessarily associated with redundancy.
One prior art antifuse cell construction 100 is shown and described with reference to FIGS. 1 and 2. Such comprises a pair of antifuse cells 102 electrically coupled together, and that individually comprise an antifuse element 104 and a transistor construction 106. Construction 100 comprises a base substrate comprising dielectric isolation regions 114 and p-type semiconductor material regions P and n-type conductively-doped n-type regions N. Transistor construction 106 comprises a gate 108, gate insulator 110, and n-type source/drain regions 112 and 113. Anti-fuse element 104 comprises a first anti-fuse electrode 120, a second anti-fuse electrode 124, and insulator material 122 there-between in the depicted “unblown” state. Gate 108 electrically couples the two antifuse cells 102 together and each antifuse cell may be separately controlled to “blow” one antifuse and not the other, or to “blow” the antifuses at different times.
Construction 100 is schematically shown as having an interconnect line 130 that connects source/drain region 112 with second anti-fuse electrode 124. A schematic interconnect line 132 connects gates 108 of transistors 106 that are adjacent to each other, left and right in FIG. 1, in an example row direction. Schematic interconnect lines 134 connect source/drain regions 113 of individual transistors 106 together, and such regions of multiple transistors in an example column direction. Schematic interconnect lines 136 connect first anti-fuse electrodes 120 of adjacent anti-fuse cells 104 together in the row direction. Schematic interconnect lines 138 connect interconnect lines 136 together in the row direction. Each of these interconnect lines is fabricated in one or more metal levels above the depicted example level of gate 108 and first anti-fuse electrode 120.